Short circuit depth variational quantum computation of Monte Carlo minimization and Nth order moments

ABSTRACT

Techniques and a system to facilitate quantum computation of Monte Carlo minimization are provided. In one example, a system includes a quantum processor and a classical processor. The quantum processor can perform an N th  order moment expectation computation process to compute an expected value of a quantum state associated with a quantum circuit description. The classical processor can execute computer executable components stored in a memory, where the computer executable components comprise a variational optimization component. The variational optimization component can perform an optimization process associated with a Monte Carlo minimization process to iteratively determine a variational parameterization for an N th  expectation value and associated trial state based on samples of the N th  order moment expectation computation process.

BACKGROUND

The subject disclosure relates generally to quantum computing. Quantum computing employs quantum physics principles to encode and manipulate information rather than relying upon classical models of computation. For example, a quantum circuit can employ quantum bits (e.g., qubits) that may be put in a superposition and/or entanglement state, based upon principles of quantum physic. The superposition principle of quantum physics allows each qubit to represent both a value of “1” and a value of “0” at the same time (along with complex valued phase). The entanglement principle of quantum physics states allows qubits to be correlated with each other in a way that has no parallel in classical computation. For instance, a state of a first value (e.g., a value of “1” or a value of “0”) can depend on a state of a second value. As such, a quantum circuit can employ qubits and quantum gates to encode information rather than binary digital techniques based classical binary bits and classical gates. A key differentiating aspect of quantum from classical computation, is that the state of an n qubit system, may require 2^(n) complex values for its representation, as opposed to n binary numbers for an n classical bits register. This exponential difference in the state space dimension, can be instrumental in acceleration of computation. However, design of a quantum circuit that leverages this advantage is generally difficult and/or time consuming as compared to conventional binary digital devices. State-of-the-art quantum devices, are not fault tolerant, which impose limitations upon the design of quantum algorithms. In one example, McClean et al., “The theory of variational hybrid quantum-classical algorithms”, discloses “a variational adiabatic ansatz and explore unitary coupled cluster where we establish a connection from second order unitary coupled cluster to universal gate sets through a relaxation of exponential operator splitting. We introduce the concept of quantum variational error suppression that allows some errors to be suppressed naturally in this algorithm on a pre-threshold quantum device. Additionally, we analyze truncation and correlated sampling in Hamiltonian averaging as ways to reduce the cost of this procedure.” However, design of a quantum circuit can be improved and/or quantum computing processing can be improved.

SUMMARY

The following presents a summary to provide a basic understanding of one or more embodiments of the invention. This summary is not intended to identify key or critical elements, or delineate any scope of the particular embodiments or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. In one or more embodiments described herein, devices, systems, computer-implemented methods, apparatus and/or computer program products for facilitating meta-level short-depth quantum computation of Monte Carlo minimization are described.

According to an embodiment, a system can comprise a quantum processor and a classical processor. The quantum processor can perform an N^(th) order moment expectation computation process to compute an expected value of a quantum state associated with a quantum circuit description, wherein N is an integer. The classical processor can execute computer executable components stored in a memory, where the computer executable components comprise a variational optimization component. The variational optimization component can perform an optimization process associated with a Monte Carlo minimization process to iteratively determine a variational parameterization for an N^(th) expectation value and associated trial state based on samples of the N^(th) order moment expectation computation process. The system can provide various advantages as compared to conventional quantum computation techniques. In certain embodiments, the system can facilitate reduction in an amount of error and/or noise associated with the quantum processor. In an embodiment, the variational optimization component can transmit the quantum circuit description to the quantum processor, and where the quantum circuit description includes a trial state variational parameterization to provide one or more advantages as compared to conventional quantum computation techniques such as, for example, facilitating reduction in an amount of error and/or noise associated with the quantum processor. In another embodiment, the quantum processor can perform the N^(th) order moment expectation computation process to generate quantum measurement data indicative of a set of quantum measurements to provide one or more advantages as compared to conventional quantum computation techniques such as, for example, facilitating reduction in an amount of error and/or noise associated with the quantum processor. In certain embodiments, the computer executable components further comprise an expectation computation component that can compute an expectation of the quantum measurement data to provide one or more advantages as compared to conventional quantum computation techniques such as, for example, facilitating reduction in an amount of error and/or noise associated with the quantum processor. In an embodiment, the variational optimization component can utilize output from the expectation of the quantum measurement data to iteratively determine a moment associated with the N^(th) order moment expectation computation process to provide one or more advantages as compared to conventional quantum computation techniques such as, for example, facilitating reduction in an amount of error and/or noise associated with the quantum processor. In another embodiment, the expectation computation component can format the quantum measurement data based on a modulo summation process to provide one or more advantages as compared to conventional quantum computation techniques such as, for example, facilitating reduction in an amount of error and/or noise associated with the quantum processor. In certain embodiments, the variational optimization component can transmit the quantum circuit description to the quantum processor to provide one or more advantages as compared to conventional quantum computation techniques such as, for example, facilitating reduction in an amount of error and/or noise associated with the quantum processor. The quantum circuit description can include an N^(th) order moment of an operator represented as a product of weighted sums of tensor products of Pauli and identity operators to provide one or more advantages as compared to conventional quantum computation techniques such as, for example, facilitating reduction in an amount of error and/or noise associated with the quantum processor. In certain embodiments, the quantum processor can perform the N^(th) order moment expectation computation process based on circuit data for describing an N^(th) order moment operator to provide one or more advantages as compared to conventional quantum computation techniques such as, for example, facilitating reduction in an amount of error and/or noise associated with the quantum processor. In certain embodiments, the variational optimization component can perform the optimization process to facilitate reduced error associated with the quantum processor.

According to another embodiment, a computer-implemented method is provided. The computer-implemented method can comprise receiving, by a system operatively coupled to a processor, samples of an N^(th) order moment expectation computation process performed by a quantum processor to compute an expected value of a quantum state associated with a quantum circuit description, wherein N is an integer. The computer-implemented method can also comprise performing, by the system, an optimization process associated with a Monte Carlo minimization process to iteratively determine a variational parameterization for a trial state based on samples of the N^(th) order moment expectation computation process. The computer-implemented method can provide various advantages as compared to conventional quantum computation techniques. In certain embodiments, the computer-implemented method can facilitate reduction in an amount of error and/or noise associated with the quantum processor. In an embodiment, the computer-implemented method can also comprise transmitting, by the system, the quantum circuit description to the quantum processor, where the quantum circuit description includes a trial state variational parameterization to provide one or more advantages as compared to conventional quantum computation techniques such as, for example, facilitating reduction in an amount of error and/or noise associated with the quantum processor. In another embodiment, the performing the optimization process can comprise performing the N^(th) order moment expectation computation process to generate quantum measurement data indicative of a set of quantum measurement to provide one or more advantages as compared to conventional quantum computation techniques such as, for example, facilitating reduction in an amount of error and/or noise associated with the quantum processor. In yet another embodiment, the computer-implemented method can also comprise computing, by the system, an expectation of the quantum measurement data to provide one or more advantages as compared to conventional quantum computation techniques such as, for example, facilitating reduction in an amount of error and/or noise associated with the quantum processor. In yet another embodiment, the computer-implemented method can also comprise utilizing, by the system, output from the expectation of the quantum measurement data to iteratively determine a moment associated with the N^(th) order moment expectation computation process to provide one or more advantages as compared to conventional quantum computation techniques such as, for example, facilitating reduction in an amount of error and/or noise associated with the quantum processor. In yet another embodiment, the performing the optimization process can comprise reducing error associated with the quantum processor.

According to yet another embodiment, a computer program product for quantum computation of Monte Carlo minimization can comprise a computer readable storage medium having program instructions embodied therewith. The program instructions can be executable by a processor and cause the processor to receive, by the processor, samples of an N^(th) order moment expectation computation process performed by a quantum processor to compute an expected value of a quantum state associated with a quantum circuit description, wherein N is an integer. The program instructions can also cause the processor to perform, by the processor, an optimization process associated with a Monte Carlo minimization process to iteratively determine a variational parameterization for a trial state based on samples of the N^(th) order moment expectation computation process. The computer program product can provide various advantages as compared to conventional quantum computation techniques. In certain embodiments, the computer program product can facilitate reduction in an amount of error and/or noise associated with the quantum processor. In an embodiment, the program instructions can also cause the processor to transmit, by the processor, the quantum circuit description to the quantum processor, wherein the quantum circuit description includes a trial state variational parameterization to provide one or more advantages as compared to conventional quantum computation techniques such as, for example, facilitating reduction in an amount of error and/or noise associated with the quantum processor. In another embodiment, the program instructions can also cause the processor to perform, by the processor, the N^(th) order moment expectation computation process to generate quantum measurement data indicative of a set of quantum measurement to provide one or more advantages as compared to conventional quantum computation techniques such as, for example, facilitating reduction in an amount of error and/or noise associated with the quantum processor. In yet another embodiment, the program instructions can also cause the processor to compute, by the system, an expectation of the quantum measurement data to provide one or more advantages as compared to conventional quantum computation techniques such as, for example, facilitating reduction in an amount of error and/or noise associated with the quantum processor. In yet another embodiment, the program instructions can also cause the processor to format, by the processor, the quantum measurement data based on a modulo summation process to provide one or more advantages as compared to conventional quantum computation techniques such as, for example, facilitating reduction in an amount of error and/or noise associated with the quantum processor.

DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a block diagram of an example, non-limiting system that includes a quantum processor and a classical processor component in accordance with one or more embodiments described herein.

FIG. 2 illustrates a block diagram of another example, non-limiting system that includes a quantum processor and a classical processor component in accordance with one or more embodiments described herein.

FIG. 3 illustrates an example, non-limiting system associated with a quantum computation process and a classical computation process in accordance with one or more embodiments described herein.

FIG. 4 illustrates example, non-limiting data in accordance with one or more embodiments described herein.

FIG. 5 illustrates a block diagram of an example, non-limiting operating environment in which one or more embodiments described herein can be facilitated.

DETAILED DESCRIPTION

The following detailed description is merely illustrative and is not intended to limit embodiments and/or application or uses of embodiments. Furthermore, there is no intention to be bound by any expressed or implied information presented in the preceding Background or Summary sections, or in the Detailed Description section.

One or more embodiments are now described with reference to the drawings, wherein like referenced numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of the one or more embodiments. It is evident, however, in various cases, that the one or more embodiments can be practiced without these specific details.

Quantum computing employs quantum physics to encode information rather than binary digital techniques based on transistors. For example, a quantum circuit can employ quantum bits (e.g., qubits) that operate according to a superposition principle of quantum physics and an entanglement principle of quantum physics. The superposition principle of quantum physics allows each qubit to represent both a value of “1” and a value of “0” at the same time. The entanglement principle of quantum physics states allows qubits in a superposition to be correlated with each other. For instance, a state of a first value (e.g., a value of “1” or a value of “0”) can depend on a state of a second value. As such, a quantum circuit can employ qubits to encode information rather than binary digital techniques based on transistors. However, design of a quantum circuit is generally difficult and/or time consuming as compared to conventional binary digital devices. Furthermore, it is generally desirable to increase efficiency of a quantum circuit and/or a quantum computing process. As such, design of a quantum circuit and/or quantum computing processing can be improved.

To address these and/or other problems associated with conventional binary digital devices, conventional quantum circuit, conventional quantum computing processing and/or other conventional technologies, embodiments described herein include systems, computer-implemented methods, and computer program products for quantum computation of Monte Carlo minimization. In an aspect, hybrid quantum and classical computation of a trial state and an expectation value associated with an N^(th) order moment expectation computation can be provided, where N is an integer. The Monte Carlo minimization can include processing a data matrix associated with quantum processing to determine a particular trial state and/or N^(th) order moment operator. In another aspect, a set of shallow depth quantum calculations can be performed in a hybrid classical computing/quantum computing environment. The set of shallow depth calculations can be, for example, calculations with a lower number of gate operations than a deep depth calculation. In another embodiment, a quantum processor can sample data associated with a quantum system based on a Monte Carlo minimization process to generate quantum measurement data. The quantum measurement data can be indicative of a set of quantum measurements associated with the data. Furthermore, a classical processor can generate statistical data indicative of an expected value associated with the quantum measurement data. The classical processor can also determine a quantum state associated with the data based on the statistical data. In an aspect, the classical processor can receive quantum measurement data from the quantum processor that can process an expectation computation. The quantum processor can also generate the quantum measurement data for a variational parametrization of a state prescription based on a Monte Carlo minimization process. In yet another embodiment, the quantum processor can perform a quantum computation in a large (e.g., 2{circumflex over ( )}n) Hilbert space. Outcomes of the quantum computation can be sampled upon n qubits. In particular, the quantum processor can perform expectation computation of an Hermitian operator with respect to a given state. In an aspect, a quantum computing execution can yield a product of an operator by a state vector and its measurement in a desired basis. The quantum expectation computation can, for example, be embedded within a classical optimization framework to perform a Monte Carlo minimization process. In certain embodiments, the quantum processor can receive an operator and a state description formatted as a sequence of quantum gates describing a state preparation, application of the operator upon the state, and/or a quantum measurement procedure.

In an embodiment, a quantum bit-string measurement can be provided to the classical processor which can compute an N^(th) order moment expectation over multiple quantum experiments of respective proposed setups. For instance, higher order moments equal to N moments can be computed where expectation of a high order operator can be utilized and repeated. In certain embodiments, to reduce circuit depth at respective expectation computations, an N^(th) order moment of an operator can be provided to a quantum computation as a product of weighted sums of tensor products of elementary quantum gates. A circuit depth computation can accommodate preparation of a state and a product of the state by a component of a decomposed operator. In certain embodiments, for a choice of an operator comprising a product of weighted sums of Pauli and identity tensor products, respective components can include a single tensor product or plural tensor products (e.g., plural tensor products smaller than a total number of terms), based upon a fidelity of the quantum processor and/or a set of precision requirements. In another aspect, a quantum state can be represented parametrically. In one example, an operator to be decomposed can be represented as a product of weighted sums (e.g., comprising Pauli operators and identities). In yet another aspect, an expectation computation by application of the operator to the state and a corresponding projection to a local measurement basis can be performed. In certain embodiments, a search (e.g., a classical computation search) can be conducted for a set of parameters that form a state that minimizes an expected value of the operator.

In another embodiment, a quantum processor can compute an expected value of a parameter-dependent deflated operator and a variationally represented quantum state. Samples of a quantum expectation computation can be employed by a Monte Carlo minimization process which iteratively determines a variational parameterization associated with one or more trial states. A classical processor can perform an optimization process that determines the variational parametrization of the quantum state that comprises a moment associated with the N^(th) order moment expectation computation process. In an aspect, a variational optimization component can send the quantum computer a quantum circuit description. The quantum circuit description can include a trial state variational parameterization. The N^(th) order moment expectation computation can include quantum measurement and can be performed on the quantum processor. Expectation of the quantum measurements output can be computed on a classical processor. The variational optimization process can utilize the quantum expectation value output functionality in a feedback mechanism to determine iteratively a moment associated with the N^(th) order moment expectation computation process. The quantum processor can compute the N^(th) order moment expectation for each component of the expectation separately, where weights of each operator component is post-multiplied classically. In one embodiment, the operator can be represented as product of weighted sums of Pauli and the identity operator, such that, effectively an overhead of a single operator per qubit is required for computation of each expectation component.

In yet another embodiment, a system can comprise a quantum processor that receives in the form of a quantum circuit, components of a trial state variational representation. The quantum computation corresponds to expectation of the operator with respect to the trial state. The measurements of the quantum computation can be provided to a classical processor that weighs the measurements according to weights of each operator component, and then compute expectation their −1 to the power of their modulo 2 sum. The classical processor can additionally perform an optimization search for a moment associated with an N^(th) order moment expectation computation process. In an aspect, a trial state and associated expectation values can be determined sequentially. Since the expectation computation may be performed on a non-fault tolerant quantum processor, the computation of the N^(th) order moment expectation of a sum of components can be replaced by the sum of multiple expectations of the components. This computation can be performed with a small overhead in terms of quantum circuit depth beyond the trial state representation, which mitigate quantum computation errors.

As such, quantum computation of Monte Carlo minimization as disclosed herein can provide various solutions to overcome the aforementioned problems associated with conventional binary digital devices, conventional quantum circuit, conventional quantum computing processing and/or other conventional technologies. For example, error (e.g., noise) associated with the quantum processor can be reduced. In another example, an amount of noise (e.g., an amount of error) associated with a non-fault tolerant quantum computation can be reduced by virtue of performing multiple short-depth circuit computation. Efficiency of the quantum processor and/or accuracy of the quantum processor can also be improved. Moreover, an amount of time to perform a quantum computation can be reduced. Furthermore, an amount of computational resources employed to compute a quantum computation can be reduced. A quantum computation can also be optimized. Additionally, accuracy of a quantum computation and/or efficiency of a quantum computation can be improved. In addition, quality of a quantum processor can be improved, performance a quantum processor can be improved, timing characteristics of a quantum processor can be improved, power characteristics of a quantum processor can be improved, and/or another characteristic of a quantum processor can be improved.

FIG. 1 illustrates a block diagram of an example, non-limiting system 100 for meta-level quantum computation in accordance with one or more embodiments described herein. In various embodiments, the system 100 can be a quantum processing system associated with technologies such as, but not limited to, quantum processing technologies, quantum circuit technologies, quantum computing design technologies, artificial intelligence technologies, machine learning technologies, search engine technologies, image recognition technologies, speech recognition technologies, model reduction technologies, iterative linear solver technologies, data mining technologies, healthcare technologies, pharmaceutical technologies, biotechnology technologies, finance technologies, chemistry technologies, material discovery technologies, vibration analysis technologies, geological technologies, aviation technologies, and/or other technologies. The system 100 can employ hardware and/or software to solve problems that are highly technical in nature, that are not abstract and that cannot be performed as a set of mental acts by a human. Further, in certain embodiments, some of the processes performed may be performed by one or more specialized computers (e.g., one or more specialized processing units, a specialized computer with a classical processor component, etc.) for carrying out defined tasks related to quantum circuit simulation. The system 100 and/or components of the system 100 can be employed to solve new problems that arise through advancements in technologies mentioned above, computer architecture, quantum processing architecture and/or the like. One or more embodiments of the system 100 can provide technical improvements to quantum processing systems, quantum circuit systems, quantum computing design systems, artificial intelligence systems, machine learning systems, search engine systems, image recognition systems, speech recognition systems, model reduction systems, iterative linear solver systems, data mining systems, healthcare systems, pharmaceutical systems, biotechnology systems, finance systems, chemistry systems, material discovery systems, vibration analysis systems, geological systems, aviation systems, and/or other systems. One or more embodiments of the system 100 can also provide technical improvements to a quantum processor (e.g., a quantum circuit) by improving processing performance of the quantum processor, improving processing efficiency of the quantum processor, improving processing accuracy of the quantum processor, improving timing characteristics of the quantum processor and/or improving power efficiency of the quantum processor.

In the embodiment shown in FIG. 1, the system 100 can include a quantum processor 102 and a classical processor component 104. As shown in FIG. 1, the classical processor component 104 can include an expectation computation component 106 and/or a variational optimization component 108. In an embodiment, the classical processor component 104 can be implemented without the expectation computation component 106. In another embodiment, the classical processor component 104 can be implemented without the variational optimization component 108. In yet another embodiment, the classical processor component 104 can be implemented with the expectation computation component 106 and the variational optimization component 108. Aspects of the classical processor component 104 can constitute machine-executable component(s) embodied within machine(s), e.g., embodied in one or more computer readable mediums (or media) associated with one or more machines. Such component(s), when executed by the one or more machines, e.g., computer(s), computing device(s), virtual machine(s), etc. can cause the machine(s) to perform the operations described. In an aspect, the classical processor component 104 can also include memory 110 that stores computer executable components and instructions. Furthermore, the classical processor component 104 can include a processor 112 to facilitate execution of the instructions (e.g., computer executable components and corresponding instructions) by the classical processor component 104. As shown, the expectation computation component 106, the variational optimization component 108, the memory 110 and/or the processor 112 can be electrically and/or communicatively coupled to one another in one or more embodiments. In an embodiment, the classical processor component 104 can be a classical processor. In another embodiment, the classical processor component 104 can be a component of a classical processor. In yet another embodiment, the classical processor component 104 can be a component in communication with a classical processor. A classical processor as disclosed herein can be a machine that processes data based on binary digits and/or transistors. Furthermore, a quantum processor as disclosed herein can be a machine that processes data based on quantum bits and/or quantum mechanical phenomena associated with superposition and/or entanglement.

The quantum processor 102 and the classical processor component 104 can be employed to provide a hybrid classical computing/quantum computing environment. For instance, the quantum processor 102 and the classical processor component 104 can be employed to perform one or more quantum computations associated with a quantum-variational architecture. The quantum processor 102 can be a machine that performs a set of calculations based on principle of quantum physics. For instance, the quantum processor 102 can perform one or more quantum computations associated with a set of quantum gates. Furthermore, the quantum processor 102 can encode information using qubits. In an aspect, the quantum processor 102 can execute a set of instruction threads associated with circuit data 114 and/or circuit data 115. In an embodiment, the quantum processor 102 can employ the circuit data 114 and/or the circuit data 115 during at least a portion of a Monte Carlo minimization process to generate quantum measurement data 116. The Monte Carlo minimization process can be a process that minimizes variance associated with the circuit data 114 and/or the circuit data 115. In one example, the Monte Carlo minimization process can be a variational Monte Carlo process that approximates a ground state of the quantum system. The circuit data 114 can be circuit data for describing a trial state associated with a quantum circuit description. The circuit data 115 can be circuit data for describing an N^(th) order moment operator associated with a quantum circuit description. The quantum processor 102 can perform an N^(th) order moment expectation computation process to compute an expected value of a quantum state associated with a quantum circuit description, where N is an integer. For instance, N number of order moments can be computed during the N^(th) order moment expectation computation process. The quantum circuit description can be described by the circuit data 114 and/or the circuit data 115. In an aspect, the quantum processor 102 can factorize the circuit data 114 and/or the circuit data 115 into a mathematical expression represented by a set of expected values and/or a set of trial states. A trial state can be a vector that can change by a scalar factor when a linear transformation is applied to the trial state. A moment expectation can be the scalar factor applied to a trial state to obtain a linear transformation. The quantum measurement data 116 can be indicative of a set of quantum measurements associated with the circuit data 114 and/or the circuit data 115. In an aspect, the quantum measurement data 116 can include a set of quantum measurements associated with the Monte Carlo minimization process. For instance, the quantum measurement data 116 can include a set of samples of the N^(th) order moment expectation computation process performed by the quantum processor 102. Furthermore, the quantum processor 102 can provide the quantum measurement data 116 to the classical processor component 104.

The classical processor component 104 can be associated with a machine that performs a set of calculations based on binary digits and/or transistors. The classical processor component 104 (e.g., the expectation computation component 106 of the classical processor component 104) can receive the quantum measurement data 116. For instance, the classical processor component 104 can be communicatively coupled to the quantum processor 102. In one example, the classical processor component 104 can be communicatively coupled to the quantum processor 102 via a wired communication channel. In another example, the classical processor component 104 can be communicatively coupled to the quantum processor 102 via a wireless communication channel.

The variational optimization component 108 can perform an optimization process associated with another portion of the Monte Carlo minimization process to iteratively determine a variational parameterization for a trial state based on the quantum measurement data 116. For instance, the variational optimization component 108 can perform an optimization process associated with another portion of the Monte Carlo minimization process to iteratively determine a variational parameterization for a trial state based on samples of the N^(th) order moment expectation computation process. In an embodiment, the variational optimization component 108 can transmit the quantum circuit description to the quantum processor 102. The quantum circuit description can include the circuit data 114 and/or the circuit data 115. For example, the quantum circuit description can include, for example, a trial state variational parameterization. In certain embodiments, the quantum circuit description can additionally or alternatively include an N^(th) order moment of an operator represented as a product of weighted sums of tensor products of Pauli and/or identity operators. The quantum processor 102 can perform the N^(th) order moment expectation computation process to generate the quantum measurement data 116. For instance, the quantum processor 102 can perform the N^(th) order moment expectation computation process to generate the quantum measurement data 116 indicative of a set of quantum measurements. The expectation computation component 106 can compute an N^(th) order moment expectation of the quantum measurement data 116. Furthermore, the variational optimization component 108 can utilize output from the N^(th) order moment expectation of the quantum measurement data 116 to iteratively determine a moment associated with the N^(th) order moment expectation computation process.

In certain embodiments, the expectation computation component 106 can generate statistical data based on the quantum measurement data 116. The statistical data can be indicative of an expected value associated with the quantum measurement data 116. For example, the expectation computation component 106 can sample one or more computations from quantum measurements associated with the quantum measurement data 116. Furthermore, the expectation computation component 106 can determine the statistical data based on the expected value of the one or more computations from the quantum measurements associated with the quantum measurement data 116. In another example, the statistical data can be indicative of a mean value associated with the quantum measurement data 116. For example, the expectation computation component 106 can sample one or more computations from quantum measurements associated with the quantum measurement data 116. Furthermore, the expectation computation component 106 can determine the statistical data based on a mean value of the one or more computations from the quantum measurements associated with the quantum measurement data 116. Additionally or alternatively, the statistical data can be indicative of another statistical value associated with the quantum measurement data 116. For example, the expectation computation component 106 can additionally or alternatively determine the statistical data based on one or more other statistical values of the one or more computations from the quantum measurements associated with the quantum measurement data 116. In certain embodiments, the expectation computation component 106 can format the quantum measurement data 116 based on a modulo summation process that employs modular arithmetic associated with a sum of two bits. The variational optimization component 108 can determine a quantum state based on the quantum measurement data 116. For instance, the variational optimization component 108 can perform a variational optimization process to facilitate determination of a quantum state based on the quantum measurement data 116. In an embodiment, the variational optimization component 108 can determine a quantum state based on the statistical data. In one example, the quantum state can include, for example, a set of quantum bits (e.g., a set of qubits). In another example, the quantum state can include information associated with an x-component measurement, a y-component measurement and/or a z-component measurement associated with a state of a quantum bit associated with the quantum processor. In an aspect, the variational optimization component 108 can determine a quantum state preparation based on the quantum measurement data 116. Additionally or alternatively, the variational optimization component 108 can determine a trial state value based on the quantum measurement data 116 and/or the statistical data. For instance, additionally or alternatively, the variational optimization component 108 can determine an N^(th) order expectation and/or associated variational description of a preparation of a trial state based on the quantum measurement data 116. In an aspect, the variational optimization component 108 can generate circuit data 118 that describes a trial state based on a variational parameterization. Additionally or alternatively, the variational optimization component 108 can generate circuit data 119 that describes an N^(th) order moment operator associated with the N^(th) order moment expectation computation process.

In certain embodiments, the expectation computation component 106 and/or the variational optimization component 108 can generate the circuit data 118 and/or the circuit data 119 based on classifications, correlations, inferences and/or expressions associated with principles of artificial intelligence. For instance, the expectation computation component 106 and/or the variational optimization component 108 can employ an automatic classification system and/or an automatic classification process to generate the circuit data 118 and/or the circuit data 119. In one example, the expectation computation component 106 and/or the variational optimization component 108 can employ a probabilistic and/or statistical-based analysis (e.g., factoring into the analysis utilities and costs) to learn and/or generate inferences with respect to the quantum measurement data 116. In an aspect, the expectation computation component 106 and/or the variational optimization component 108 can include an inference component (not shown) that can further enhance aspects of the expectation computation component 106 and/or the variational optimization component 108 utilizing in part inference based schemes to facilitate learning and/or generating inferences associated with the quantum measurement data 116. The expectation computation component 106 and/or the variational optimization component 108 can employ any suitable machine-learning based techniques, statistical-based techniques and/or probabilistic-based techniques. For example, the expectation computation component 106 and/or the variational optimization component 108 can employ expert systems, fuzzy logic, SVMs, Hidden Markov Models (HMMs), greedy search algorithms, rule-based systems, Bayesian models (e.g., Bayesian networks), neural networks, other non-linear training techniques, data fusion, utility-based analytical systems, systems employing Bayesian models, etc. In another aspect, the expectation computation component 106 and/or the variational optimization component 108 can perform a set of machine learning computations associated with generation of the circuit data 118 and/or the circuit data 119. For example, the expectation computation component 106 and/or the variational optimization component 108 can perform a set of clustering machine learning computations, a set of logistic regression machine learning computations, a set of decision tree machine learning computations, a set of random forest machine learning computations, a set of regression tree machine learning computations, a set of least square machine learning computations, a set of instance-based machine learning computations, a set of regression machine learning computations, a set of support vector regression machine learning computations, a set of k-means machine learning computations, a set of spectral clustering machine learning computations, a set of rule learning machine learning computations, a set of Bayesian machine learning computations, a set of deep Boltzmann machine computations, a set of deep belief network computations, and/or a set of different machine learning computations to generate the circuit data 118 and/or the circuit data 119.

It is to be appreciated that the quantum processor 102 and/or the classical processor component 104 (e.g., the expectation computation component 106 and/or the variational optimization component 108) performs one or more quantum computation processes that cannot be performed by a human (e.g., is greater than the capability of a single human mind). For example, an amount of data processed, a speed of data processed and/or data types of data processed by the quantum processor 102 and/or the classical processor component 104 (e.g., the expectation computation component 106 and/or the variational optimization component 108) over a certain period of time can be greater, faster and different than an amount, speed and data type that can be processed by a single human mind over the same period of time. The quantum processor 102 and/or the classical processor component 104 (e.g., the expectation computation component 106 and/or the variational optimization component 108) can also be fully operational towards performing one or more other functions (e.g., fully powered on, fully executed, etc.) while also performing the above-referenced quantum circuit decomposition process and/or one or more simulation processes. Moreover, the quantum measurement data 116, the circuit data 118 and/or the circuit data 119 generated by the quantum processor 102 and/or the classical processor component 104 (e.g., the expectation computation component 106 and/or the variational optimization component 108) can include information that is impossible to obtain manually by a user. For example, a type of information included in the quantum measurement data 116, the circuit data 118 and/or the circuit data 119, and/or a variety of information included in the quantum measurement data 116, the circuit data 118 and/or the circuit data 119 can be more complex than information obtained manually by a user.

Additionally, it is to be appreciated that the system 100 can provide various advantages as compared to conventional quantum computation techniques. The system 100 can also provide various solutions to problems associated with conventional quantum computation techniques. For instance, an amount of time to perform a quantum computation process can be reduced by employing the system 100. Furthermore, an amount of computational resources employed to perform a quantum computation process can be reduced by employing the system 100. Accuracy of a quantum computation can also be improved by employing the system 100. Additionally, an amount of error and/or noise associated with a quantum computation can be reduced by employing the system 100. Additionally, an amount of error and/or noise associated with a quantum processor can be reduced by employing the system 100. Moreover, quality of a quantum processor can be improved, performance a quantum processor can be improved, efficiency of a quantum processor can be improved, timing characteristics of a quantum processor can be improved, power characteristics of a quantum processor can be improved, and/or another characteristic of a quantum processor can be improved by employing the system 100.

FIG. 2 illustrates a block diagram of an example, non-limiting system 200 in accordance with one or more embodiments described herein. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

The system 200 includes the quantum processor 102 and the classical processor component 104. The classical processor component 104 can include the expectation computation component 106, the variational optimization component 108, the memory 110 and/or the processor 112. The quantum processor 102 shown in FIG. 2 can execute a Monte Carlo minimization process 202. The quantum processor 102 can employ the Monte Carlo minimization process 202 to generate the quantum measurement data 116. In an aspect, the Monte Carlo minimization process 202 can be a Monte Carlo minimization process for an N^(th) order moment expectation computation. For example, the Monte Carlo minimization process 202 can include trial state preparation and/or an N^(th) order moment expectation realization process to compute a moment associated with a trial state. In one example, the Monte Carlo minimization process 202 can generate a set of quantum measurements associated with the circuit data 114 and/or the circuit data 115.

In an embodiment, the Monte Carlo minimization process 202 can be a process that minimizes variance associated with the circuit data 114 and/or the circuit data 115. In one example, the Monte Carlo minimization process 202 can be a variational Monte Carlo process that approximates a ground state of a quantum system associated with the circuit data 114 and/or the circuit data 115. In one example, the Monte Carlo minimization process 202 can generate a set of quantum measurements associated with the circuit data 114 and/or the circuit data 115. In an embodiment, the Monte Carlo minimization process 202 can employ data to minimize variance associated with the circuit data 114 and/or the circuit data 115. For example, the Monte Carlo minimization process 202 can combine a first computation associated with a quantum variational estimator of second moment minus a square of a second computation associated with a quantum variational estimator of first moment to determine variance minimization. In an aspect, the Monte Carlo minimization process 202 can combine a computation of a second moment minus a square of a first moment via a variance minimization procedure. In an embodiment, the Monte Carlo minimization process 202 can be a Monte Carlo variance estimate that corresponds to:

V min ⁡ ( ) = min | ψ 〉 ⁢ 〈 ψ ⁢  2  ⁢ ψ 〉 〈 ψ | ψ 〉 - 〈 ψ ⁢   ⁢ ψ 〉 2 〈 ψ | ψ 〉

Additionally, it is to be appreciated that the system 200 can provide various advantages as compared to conventional quantum computation techniques. The system 100 can also provide various solutions to problems associated with conventional quantum computation techniques. For instance, an amount of time to perform a quantum computation process can be reduced by employing the system 200. Furthermore, an amount of computational resources employed to perform a quantum computation process can be reduced by employing the system 200. Accuracy of a quantum computation can also be improved by employing the system 200. Additionally, an amount of error and/or noise associated with a quantum computation can be reduced by employing the system 200. Additionally, an amount of error and/or noise associated with a quantum processor can be reduced by employing the system 200. Moreover, quality of a quantum processor can be improved, performance a quantum processor can be improved, efficiency of a quantum processor can be improved, timing characteristics of a quantum processor can be improved, power characteristics of a quantum processor can be improved, and/or another characteristic of a quantum processor can be improved by employing the system 200.

FIG. 3 illustrates an example, non-limiting system 300 in accordance with one or more embodiments described herein. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

The system 300 can include a quantum computation process 302 and a classical computation process 304. The quantum computation process 302 can be executed by a quantum processor and the classical computation process can be performed by a classical processor. In an aspect, the quantum computation process 302 can be associated with the quantum processor 102 and the classical computation process 304 can be associated with the classical processor component 104. The quantum computation process 302 can include a trial state preparation process 306, an N^(th) order moment expectation computation process 307 and/or an expectation realization process 308. The trial state preparation process 306 can provide a set of gates to load onto a quantum processor (e.g., the quantum processor 102). The trial state preparation process 306 can also enable a quantum processor (e.g., the quantum processor 102) with one or more trial states tailored for a set of interactions associated with the quantum processor (e.g., the quantum processor 102). In a non-limiting example, the trial state preparation process 306 can be characterized by the following equation: |ψ(0 ^(k)))

The N^(th) order moment expectation computation process 307 can compute an N^(th) order moment expected value of a quantum state associated with a quantum circuit description. In an embodiment, the N^(th) order moment expectation computation process 307 can correspond to:

〈 v ⁡ ( θ ) ⁢  N  ⁢ v ⁡ ( θ ) 〉 = 〈 v ⁡ ( θ ) ⁢  ∑ i , j ⁢ w i ⁢ w j ⁢ q i ⁢ q j  ⁢ v ⁡ ( θ ) 〉 = ∑ i , j ⁢ w i ⁢ w j ( v ⁡ ( θ ) ⁢  q i ⁢ q j  ⁢ v ⁡ ( θ ) 〉

The expectation realization process 308 can perform at least a portion of a Monte Carlo minimization process (e.g., the Monte Carlo minimization process 202). In an aspect, the expectation realization process 308 can determine a set of expectation values for terms in a qubit Hamiltonian. Additionally, or alternatively, the expectation realization process 308 can estimate energy of a trial state associated with the trial state preparation process 306. In one example, the expectation realization process 308 can estimate energy of a trial state associated with the trial state preparation process 306 by measuring a set of expectation values of a set of Pauli terms in the Hamiltonian. In a non-limiting example, the expectation realization process 308 can be characterized by the following equation:

ψ(0 ^((k)))|

γ|ψ(0 ^((k)))

The classical computation process 304 can be performed based on the quantum computation process 302. For example, the classical computation process 304 can be performed based on quantum measurement data (e.g., the quantum measurement data 116) associated with the quantum computation process 302. The classical computation process 304 can include an N^(th) order moment expectation of quantum measurement process 310, a sample expectation process 312 and/or an optimization process 314. The N^(th) order moment expectation of quantum measurement process 310 can format data provided by the quantum computation process 302. For instance, the N^(th) order moment expectation of quantum measurement process 310 can format quantum measurement data (e.g., the quantum measurement data 116) associated with the quantum computation process 302. In one example, the N^(th) order moment expectation of quantum measurement process 310 can format data provided by the quantum computation process 302 based on a modulo summation process. In one example, the modulo summation process can be a modulo 2 summation process. The sample expectation process 312 can generate statistical data associated with data provided by the quantum computation process 302. For example, the sample expectation process 312 can generate statistical data associated with quantum measurement data (e.g., the quantum measurement data 116) determined by the quantum computation process 302. In an embodiment, the sample expectation process 312 can generate expectation data indicative of one or more expected values associated with data provided by the quantum computation process 302. In another embodiment, the sample expectation process 312 can generate mean data indicative of one or more mean values associated with data provided by the quantum computation process 302. The optimization process 314 can optimize data provided by the quantum computation process 302 to determine variational parametrization associated with the data. In an embodiment, the optimization process 314 can employ one or more derivative free optimization techniques, a template based pattern search, derivative based optimization, mixed integer non-linear programming and/or another technique to optimize data provided by the quantum computation process 302. In one example, the quantum computation process 302 can determine a cost function associated with the quantum processor (e.g., the quantum processor 102). The cost function can be associated with energy associated with the quantum processor (e.g., the quantum processor 102), for example. Furthermore, based on the cost function, the quantum computation process 302 can adjust a set of variational parameters. In an embodiment, the set of variational parameters can be provided to the trial state preparation process 306 as feedback data to reduce the cost function associated with the quantum processor (e.g., the quantum processor 102).

FIG. 4 illustrates example, non-limiting data 400 in accordance with one or more embodiments described herein. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

The data 400 can be, for example, data employed by a classical processor. For instance, the data 400 can be converted into a different data format (e.g., a product of weighted sums of tensor products of Pauli operators) that is provided to a quantum processor (e.g., quantum processor 102). In one example, the data 400 can be data provided to a quantum processor (e.g., quantum processor 102) after being transformed into a suitable format for processing by the quantum processor. In an embodiment, the data 400 can be formatted as a data matrix. For example, the data 400 can be formatted as an 8×8 data matrix. In another embodiment, the data 400 can be formatted as a weighted sum of products of Pauli operators that start from an initial data matrix description. The data 400 can be associated with a quantum system that performs one or more quantum computations. In an aspect, the data 400 can be associated with a quantum processing system, a quantum circuit system, a quantum computing design system, an artificial intelligence system, a machine learning system, a search engine system, an image recognition system, a speech recognition system, a model reduction system, an iterative linear solver system, a data mining system, a healthcare system, a pharmaceutical system, a biotechnology system, a finance system, a chemistry system, a material discovery system, a vibration analysis system, a geological system, an aviation system and/or another system. In an embodiment, the data 400 can be processed by a Monte Carlo minimization process (e.g., the Monte Carlo minimization process 202). In an embodiment, an N^(th) order expectation of the data 400 can be determined with three qubits associated with a quantum processor (e.g., the quantum processor 102) since the data 400 is an 8 by 8 matrix and log 28=3.

Moreover, because at least generating statistical data associated with quantum measurement data, determining a quantum state associated with data, etc. are established from a combination of electrical and mechanical components and circuitry, a human is unable to replicate or perform processing performed by the classical processor component 104 (e.g., the expectation computation component 106 and/or the variational optimization component 108) disclosed herein. For example, a human is unable to determine a quantum data for data associated with a quantum processor, etc.

In order to provide a context for the various aspects of the disclosed subject matter, FIG. 5 as well as the following discussion are intended to provide a general description of a suitable environment in which the various aspects of the disclosed subject matter can be implemented. FIG. 5 illustrates a block diagram of an example, non-limiting operating environment in which one or more embodiments described herein can be facilitated. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

With reference to FIG. 5, a suitable operating environment 500 for implementing various aspects of this disclosure can also include a computer 512. The computer 512 can also include a processing unit 514, a system memory 516, and a system bus 518. The system bus 518 couples system components including, but not limited to, the system memory 516 to the processing unit 514. The processing unit 514 can be any of various available processors. Dual microprocessors and other multiprocessor architectures also can be employed as the processing unit 514. The system bus 518 can be any of several types of bus structure(s) including the memory bus or memory controller, a peripheral bus or external bus, and/or a local bus using any variety of available bus architectures including, but not limited to, Industrial Standard Architecture (ISA), Micro-Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), Firewire (IEEE 1394), and Small Computer Systems Interface (SCSI).

The system memory 516 can also include volatile memory 520 and nonvolatile memory 522. The basic input/output system (BIOS), containing the basic routines to transfer information between elements within the computer 512, such as during start-up, is stored in nonvolatile memory 522. Computer 512 can also include removable/non-removable, volatile/non-volatile computer storage media. FIG. 5 illustrates, for example, a disk storage 524. Disk storage 524 can also include, but is not limited to, devices like a magnetic disk drive, floppy disk drive, tape drive, Jaz drive, Zip drive, LS-100 drive, flash memory card, or memory stick. The disk storage 524 also can include storage media separately or in combination with other storage media. To facilitate connection of the disk storage 524 to the system bus 518, a removable or non-removable interface is typically used, such as interface 526. FIG. 5 also depicts software that acts as an intermediary between users and the basic computer resources described in the suitable operating environment 500. Such software can also include, for example, an operating system 528. Operating system 528, which can be stored on disk storage 524, acts to control and allocate resources of the computer 512.

System applications 530 take advantage of the management of resources by operating system 528 through program modules 532 and program data 534, e.g., stored either in system memory 516 or on disk storage 524. It is to be appreciated that this disclosure can be implemented with various operating systems or combinations of operating systems. A user enters commands or information into the computer 512 through input device(s) 536. Input devices 536 include, but are not limited to, a pointing device such as a mouse, trackball, stylus, touch pad, keyboard, microphone, joystick, game pad, satellite dish, scanner, TV tuner card, digital camera, digital video camera, web camera, and the like. These and other input devices connect to the processing unit 514 through the system bus 518 via interface port(s) 538. Interface port(s) 538 include, for example, a serial port, a parallel port, a game port, and a universal serial bus (USB). Output device(s) 540 use some of the same type of ports as input device(s) 536. Thus, for example, a USB port can be used to provide input to computer 512, and to output information from computer 512 to an output device 540. Output adapter 542 is provided to illustrate that there are some output devices 540 like monitors, speakers, and printers, among other output devices 540, which require special adapters. The output adapters 542 include, by way of illustration and not limitation, video and sound cards that provide a means of connection between the output device 540 and the system bus 518. It should be noted that other devices and/or systems of devices provide both input and output capabilities such as remote computer(s) 544.

Computer 512 can operate in a networked environment using logical connections to one or more remote computers, such as remote computer(s) 544. The remote computer(s) 544 can be a computer, a server, a router, a network PC, a workstation, a microprocessor based appliance, a peer device or other common network node and the like, and typically can also include many or all of the elements described relative to computer 512. For purposes of brevity, only a memory storage device 546 is illustrated with remote computer(s) 544. Remote computer(s) 544 is logically connected to computer 512 through a network interface 548 and then physically connected via communication connection 550. Network interface 548 encompasses wire and/or wireless communication networks such as local-area networks (LAN), wide-area networks (WAN), cellular networks, etc. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, Token Ring and the like. WAN technologies include, but are not limited to, point-to-point links, circuit switching networks like Integrated Services Digital Networks (ISDN) and variations thereon, packet switching networks, and Digital Subscriber Lines (DSL). Communication connection(s) 550 refers to the hardware/software employed to connect the network interface 548 to the system bus 518. While communication connection 550 is shown for illustrative clarity inside computer 512, it can also be external to computer 512. The hardware/software for connection to the network interface 548 can also include, for exemplary purposes only, internal and external technologies such as, modems including regular telephone grade modems, cable modems and DSL modems, ISDN adapters, and Ethernet cards.

The present invention may be a system, a method, an apparatus and/or a computer program product at any possible technical detail level of integration. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention. The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium can also include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. A network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing device. Computer readable program instructions for carrying out operations of the present invention can be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuitry, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++, or the like, and procedural programming languages, such as the “C” programming language or similar programming languages. The computer readable program instructions can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present invention.

Aspects of the present invention are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer readable program instructions. These computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks. The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational acts to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams can represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the blocks can occur out of the order noted in the Figures. For example, two blocks shown in succession can, in fact, be executed substantially concurrently, or the blocks can sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.

While the subject matter has been described above in the general context of computer-executable instructions of a computer program product that runs on a computer and/or computers, those skilled in the art will recognize that this disclosure also can or can be implemented in combination with other program modules. Generally, program modules include routines, programs, components, data structures, etc. that perform particular tasks and/or implement particular abstract data types. Moreover, those skilled in the art will appreciate that the inventive computer-implemented methods can be practiced with other computer system configurations, including single-processor or multiprocessor computer systems, mini-computing devices, mainframe computers, as well as computers, hand-held computing devices (e.g., PDA, phone), microprocessor-based or programmable consumer or industrial electronics, and the like. The illustrated aspects can also be practiced in distributed computing environments in which tasks are performed by remote processing devices that are linked through a communications network. However, some, if not all aspects of this disclosure can be practiced on stand-alone computers. In a distributed computing environment, program modules can be located in both local and remote memory storage devices.

As used in this application, the terms “component,” “system,” “platform,” “interface,” and the like, can refer to and/or can include a computer-related entity or an entity related to an operational machine with one or more specific functionalities. The entities disclosed herein can be either hardware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a server and the server can be a component. One or more components can reside within a process and/or thread of execution and a component can be localized on one computer and/or distributed between two or more computers. In another example, respective components can execute from various computer readable media having various data structures stored thereon. The components can communicate via local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and/or across a network such as the Internet with other systems via the signal). As another example, a component can be an apparatus with specific functionality provided by mechanical parts operated by electric or electronic circuitry, which is operated by a software or firmware application executed by a processor. In such a case, the processor can be internal or external to the apparatus and can execute at least a part of the software or firmware application. As yet another example, a component can be an apparatus that provides specific functionality through electronic components without mechanical parts, wherein the electronic components can include a processor or other means to execute software or firmware that confers at least in part the functionality of the electronic components. In an aspect, a component can emulate an electronic component via a virtual machine, e.g., within a cloud computing system.

In addition, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless specified otherwise, or clear from context, “X employs A or B” is intended to mean any of the natural inclusive permutations. That is, if X employs A; X employs B; or X employs both A and B, then “X employs A or B” is satisfied under any of the foregoing instances. Moreover, articles “a” and “an” as used in the subject specification and annexed drawings should generally be construed to mean “one or more” unless specified otherwise or clear from context to be directed to a singular form. As used herein, the terms “example” and/or “exemplary” are utilized to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited by such examples. In addition, any aspect or design described herein as an “example” and/or “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects or designs, nor is it meant to preclude equivalent exemplary structures and techniques known to those of ordinary skill in the art.

As it is employed in the subject specification, the term “processor” can refer to substantially any computing processing unit or device comprising, but not limited to, single-core processors; single-processors with software multithread execution capability; multi-core processors; multi-core processors with software multithread execution capability; multi-core processors with hardware multithread technology; parallel platforms; and parallel platforms with distributed shared memory. Additionally, a processor can refer to an integrated circuit, an application specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), a discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Further, processors can exploit nano-scale architectures such as, but not limited to, molecular and quantum-dot based transistors, switches and gates, in order to optimize space usage or enhance performance of user equipment. A processor can also be implemented as a combination of computing processing units. In this disclosure, terms such as “store,” “storage,” “data store,” data storage,” “database,” and substantially any other information storage component relevant to operation and functionality of a component are utilized to refer to “memory components,” entities embodied in a “memory,” or components comprising a memory. It is to be appreciated that memory and/or memory components described herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of illustration, and not limitation, nonvolatile memory can include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or nonvolatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM). Volatile memory can include RAM, which can act as external cache memory, for example. By way of illustration and not limitation, RAM is available in many forms such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM). Additionally, the disclosed memory components of systems or computer-implemented methods herein are intended to include, without being limited to including, these and any other suitable types of memory.

What has been described above include mere examples of systems and computer-implemented methods. It is, of course, not possible to describe every conceivable combination of components or computer-implemented methods for purposes of describing this disclosure, but one of ordinary skill in the art can recognize that many further combinations and permutations of this disclosure are possible. Furthermore, to the extent that the terms “includes,” “has,” “possesses,” and the like are used in the detailed description, claims, appendices and drawings such terms are intended to be inclusive in a manner similar to the term “comprising” as “comprising” is interpreted when employed as a transitional word in a claim.

The descriptions of the various embodiments have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein. 

What is claimed is:
 1. A system, comprising: a quantum processor that performs an N^(th) order moment expectation computation process to compute an expected value of a quantum state associated with a quantum circuit description, wherein N is an integer; and a classical processor that executes computer executable components stored in a memory, wherein the computer executable components comprise: a variational optimization component that performs an optimization process comprising a Monte Carlo minimization process to iteratively determine a variational parameterization for an N^(th) expectation value and associated trial state based on samples of the N^(th) order moment expectation computation process.
 2. The system of claim 1, wherein the variational optimization component transmits the quantum circuit description to the quantum processor, and wherein the quantum circuit description includes a trial state variational parameterization.
 3. The system of claim 2, wherein the quantum processor performs the N^(th) order moment expectation computation process to generate quantum measurement data indicative of a set of quantum measurements.
 4. The system of claim 3, wherein the computer executable components further comprise: an expectation computation component that computes an expectation of the quantum measurement data.
 5. The system of claim 4, wherein the variational optimization component utilizes output from the expectation of the quantum measurement data to iteratively determine a moment associated with the N^(th) order moment expectation computation process.
 6. The system of claim 4, wherein expectation computation component formats the quantum measurement data based on a modulo summation process.
 7. The system of claim 1, wherein the variational optimization component transmits the quantum circuit description to the quantum processor, and wherein the quantum circuit description includes an N^(th) order moment of an operator represented as a product of weighted sums of tensor products of Pauli and identity operators.
 8. The system of claim 1, wherein the quantum processor performs the N^(th) order moment expectation computation process based on circuit data for describing an N^(th) order moment operator.
 9. The system of claim 1, wherein the variational optimization component performs the optimization process to facilitate reduced error associated with the quantum processor.
 10. A computer-implemented method, comprising: receiving, by a system operatively coupled to a processor, samples of an N^(th) order moment expectation computation process performed by a quantum processor to compute an expected value of a quantum state associated with a quantum circuit description, wherein N is an integer; and performing, by the system, an optimization process comprising a Monte Carlo minimization process to iteratively determine a variational parameterization for a trial state based on samples of the N^(th) order moment expectation computation process.
 11. The computer-implemented method of claim 10, further comprising: transmitting, by the system, the quantum circuit description to the quantum processor, wherein the quantum circuit description includes a trial state variational parameterization.
 12. The computer-implemented method of claim 11, wherein the performing the optimization process comprises performing the N^(th) order moment expectation computation process to generate quantum measurement data indicative of a set of quantum measurement.
 13. The computer-implemented method of claim 12, further comprising: computing, by the system, an expectation of the quantum measurement data.
 14. The computer-implemented method of claim 13, further comprising: utilizing, by the system, output from the expectation of the quantum measurement data to iteratively determine a moment associated with the N^(th) order moment expectation computation process.
 15. The computer-implemented method of claim 10, wherein the performing the optimization process comprises reducing error associated with the quantum processor.
 16. A computer program product for quantum computation of Monte Carlo minimization, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to: receive, by the processor, samples of an N^(th) order moment expectation computation process performed by a quantum processor to compute an expected value of a quantum state associated with a quantum circuit description, wherein N is an integer; and perform, by the processor, an optimization process comprising a Monte Carlo minimization process to iteratively determine a variational parameterization for a trial state based on samples of the N^(th) order moment expectation computation process.
 17. The computer program product of claim 16, wherein the program instructions are further executable by the processor to cause the processor to: transmit, by the processor, the quantum circuit description to the quantum processor, wherein the quantum circuit description includes a trial state variational parameterization.
 18. The computer program product of claim 17, wherein the program instructions are further executable by the processor to cause the processor to: perform, by the processor, the N^(th) order moment expectation computation process to generate quantum measurement data indicative of a set of quantum measurement.
 19. The computer program product of claim 18, wherein the program instructions are further executable by the processor to cause the processor to: compute, by the processor, an expectation of the quantum measurement data.
 20. The computer program product of claim 18, wherein the program instructions are further executable by the processor to cause the processor to: format, by the processor, the quantum measurement data based on a modulo summation process. 